A liquid crystal display panel used in a liquid crystal display device includes a TFT substrate in which pixels each having a pixel electrode, a thin film transistor (TFT), and the like, are arranged in a matrix form. A counter substrate is disposed opposite to the TFT substrate, in which color filters, and the like, are formed at positions corresponding to the pixel electrodes of the TFT substrate. Further, a liquid crystal is interposed between the TFT substrate and the counter substrate. Thus, the liquid crystal display panel is designed to form an image by controlling the transmittance of light of the liquid crystal molecules for each pixel.
The liquid crystal display device is flat and light weight, and is used in a wide range of applications in various fields. Small liquid crystal display devices are widely used in portable electronic devices such as mobile phones and digital still cameras (DSC). In the case of the liquid crystal display device, viewing angle characteristics are a problem. The viewing angle is a phenomenon in which the brightness changes or the color changes between when the display is viewed from the front, and when the display is viewed from an oblique direction. The viewing angle characteristics are excellent in the in plane switching (IPS) mode to drive liquid crystal molecules by the electric field in the horizontal direction.
There are many different types of IPS mode. For example, a common electrode or a pixel electrode is formed in a planar shape, on which a comb-like pixel electrode or common electrode is disposed with an insulating film interposed therebetween. In this way, the liquid crystal molecules are rotated by an electric field generated between the pixel electrode and the common electrode. This type can increase the transmittance and is currently a mainstream IPS mode.
The above type of IPS has been configured as follows. First, a TFT is formed. Then, the TFT is covered by a passivation film, on which a common electrode, an insulating film, a pixel electrode, and the like, are formed. However, there is a requirement to reduce production costs. So it is designed to reduce the number of layers disposed on the TFT substrate, such as the conductive film and the insulating film.
As an example of the IPS mode in which the common electrode is formed on the lower layer of the passivation film, JP-A No. 168878/2009 describes a configuration in which a common electrode is formed on the same layer as a gate electrode. Then, a comb-like pixel electrode is formed between a gate insulating film and a protective insulating film.
FIG. 5 is a cross-sectional view of a TFT substrate 100 of IPS mode to which the present invention is applied. FIG. 5 shows a configuration in which the number of layers is reduced in the IPS mode. Note that the configuration of FIG. 5 is different from the configuration of the IPS described in JP-A No. 168878/2009. In FIG. 5, a gate electrode 101 is formed on the TFT substrate 100 of glass. The gate electrode 101 is formed, for example, by depositing MoCr on AlNd alloy. A gate insulating film 102 is formed by sputtering SiN on the gate electrode 101.
A semiconductor layer 103 is formed on the gate insulating film 102 above the gate electrode 101. An a-Si film is formed as the semiconductor layer 103 by CVD. A drain electrode 104 and a source electrode 105 are placed opposite to each other on the semiconductor layer 103. The drain electrode 104 and the source electrode 105 are simultaneously formed from MoCr. The area between the drain electrode 104 and the source electrode 105 is a channel layer in the TFT. Note that in order to achieve ohmic contact, an n+Si layer not shown is formed between the semiconductor layer 103 and the drain electrode 104 or the source electrode 105.
In FIG. 5, after the formation of the drain electrode 104 or the source electrode 105, a pixel electrode 106 is formed from ITO in a planar shape. A portion of the pixel electrode 106 is overlapped with the source electrode 105 to establish electrical contact between the pixel electrode 106 and the source electrode 105. Then, a passivation film 107 is formed to cover the drain electrode 104, the source electrode 105, the pixel electrode 106, and the like. The passivation film 107 is formed from SiN by CVD. Normally, the passivation film 107 is to protect the TFT. In FIG. 5, however, the passivation film 107 also serves as an insulating film between a common electrode 108 and the pixel electrode 106.
The common electrode 108 is formed in a comb-like shape on the passivation film 107. Further, an oriented film not shown is formed on the common electrode 108. Then, a liquid crystal layer is present on the oriented film. The liquid crystal layer is interposed between the TFT substrate 100 and a counter substrate, not shown, on which color filters and the like are formed. In FIG. 5, T represents the area in which the TFT is formed, S represents the area in which the source electrode 105 is formed, P represents the area in which the pixel electrode 106 is formed, and D represents the area in which an image signal line 20 is formed.
FIG. 6 is a top view of the TFT, the pixel electrode 106, the common electrode 108, and the like. In FIG. 6, the semiconductor layer 103 is formed on the gate electrode 101. The drain electrode 104 and the source electrode 105 are placed opposite to each other on the semiconductor layer 103. The drain electrode 104 is a branch of the image signal line 20. The gate electrode 101 is a branch of a scan line 10.
In FIG. 6, the pixel electrode 106 is formed in a rectangular shape. A portion of the pixel electrode 106 covers a portion of the source electrode 105 to establish contact between the pixel electrode 106 and the source electrode 105. The comb-like common electrode 108 is placed on the rectangular pixel electrode 106 with the passivation film 107 not shown interposed therebetween.
When an electric field is applied between the common electrode 108 and the pixel electrode 106, the liquid crystal molecules are rotated by the lateral component of the electric field. In this way, the transmittance of the backlight is controlled in each pixel to form an image.
FIGS. 7A, 7B, 7C are views of the problem with such a configuration as shown in FIG. 6. The patterning of the pixel electrode 106 is performed by photolithography. More specifically, after coating of a resist 200 which is, for example, a negative resist, the necessary part of the resist 200 is exposed so as to be insoluble in a developer 300. The part of the resist 200 without being exposed is removed by the developer 300. During the resist is removed by the developer or after the resist is removed, the ITO is exposed in the stripper for a certain period of time. If there is a pin hole in the ITO, cell reaction occurs between ITO and MoCr due to the existence of the developer in the portion of the pin hole. As a result, the MoCr is rapidly etched and disappears.
FIG. 7A, 7B, 7C are views of this phenomenon. FIG. 7A shows the sate in which a pin hole 1061 is present in the pixel electrode 106, which is formed from ITO, in the area where the resist 200 is not present. When the resist is of the negative type, the portion of the resist 200 where the ITO should remain is exposed to be insoluble in the developer 300. The other portion of the resist 200 is dissolved in the developer 300. FIG. 7B shows the state in which the developer 300 is present.
In FIG. 7B, the developer 300 directly comes into contact with the source electrode 105 through the ITO pin hole. At this time, cell reaction occurs between the ITO and the MoCr forming the source electrode 105 through the developer 300. The source electrode 105 is etched rapidly. Then, as shown in FIG. 7C, the source electrode 105 disappears in the ITO pin hole. This phenomenon could possibly cause disconnection of the source electrode 105.
The foregoing description focuses on the problem of the portion of the source electrode 105. However, since the source electrode 105, the drain electrode 104, and the image signal line 20 are formed on the same layer, the same problem can also occur in the image signal line 20, the drain electrode 104, and the like. In particular, this problem is serious in the image signal line 20 because it is narrow and long. In other words, the image signal lien 20 is more likely to be disconnected. This leads to the risk of a low production yield as well as a low reliability.